ID-Substrate is a sign-off and verification tool that uniquely captures and simulates all substrate parasitic circuits with SPICE accuracy. ID-Substrate detects parasitic effects that are normally found after fabrication. It is the very last step before the tapeout – a ‘sanity-check’ giving the designer a chance to go back to his layout our even schematic and eliminate the costly substrate failure risks while the cost is still insignificant. With ID-Substrate, rest assured that the design sent to tapeout will have no reliability issues nor catastrofic failures. Good-bye latch-up! ID-Substrate thorougly checks all the areas of the substrate and gives the result in minutes: unlike existing tools, which use inefficient finite-element analysis techniques, ID-Substrate operates at a fraction of the time, providing the right information to prevent substrate coupling issues and catastrophic latch-up failure in Power ICs. ID-Substrate can also be used to verify if further area reduction is possible without inducing reliability risks. ID-Substrate Benefits Accurate simulate local minority, majority and total substrate-currents Quickly show any high-risk substrate current “hot spots” Verify the effectiveness of your guard-ring isolation strategies Simulate substrate + schematic and prevent catastrophic latch-up failure Easily assess block-level or system-level analog schematic circuits ID-Substrate Features Adaptive meshing ensures fast operations and accurate modelling Controlled regional meshing for precise analysis, at the best speed Operates with the Cadence Analog Design environment Simulates substrate with the extracted schematic, for complete parasitic capture
